XPC850ZT50BU Datasheet, PDF (34/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Layout Practices
1 _{The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as}
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no
direct relation with the total system interrupt latency that the MPC850 is able to support
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MPC850 (Rev. A/B/C) Hardware Specifications
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