SDA9380-B21 Datasheet, PDF (57/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
Recommended operating conditions
Parameter
Symbol Min Nom Max
Slope
IIC bus: peak drive limit B1,B0
10
11
00
01
0.125
0.375
0.625
0.875
Blue stretch (control bit BLUES; subaddress 20h)
Decrease of small signal gain for red
17
and green at nominal input amplitu-
des and nominal settings of contrast
and brightness
Percentage of nominal input voltage
80
at which decrease of gain begins
(nominal settings of contrast and
brightness)
Unit Remark
%
%
I²C Bus (all values are referred to min(V_IH) and max(V_IL))
SCL clock frequency
f_SCL
0
High-level input voltage
V_IH
0.75*
V_DD(D)
Low-level input voltage
V_IL
0
Load capacitance
C_b
Rise times of SCL, SDA
t_R
20+0.1*
C_b/pF*)
Fall times of SCL, SDA
t_F
20+0.1*
C_b/pF*)
Set-up time DATA
t_SU;DAT
100
Hold time DATA
t_HD;DAT
0
Spike duration at inputs
C_b
0
*) Fast-mode (f_SCL = 400 kHz)
400 kHz
5.25 V
1.5
V
400 pF
300*) ns
300 ns
ns
ns
50
ns
Micronas
8-49
2001-01-29