SDA9380-B21 Datasheet, PDF(13/72 Page) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

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SDA9380-B21 Datasheet, PDF (13/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

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SDA 9380 - B21

Preliminary Data Sheet

Pin configuration

4.1 Pin description

Pin No.

Name

CLKI

CLEXT

TEST

SUBST

RESN

SCL

SDA

VDD(D)

VSS(D)

H35K

H38K

PWM

VSYNC

FH1_2

HSYNC

VDD(A1)

VSS(A1)

Î¦2

VDD(A2)

VSS(A2)

E/W

D/A

VD+

VD-

VDD(A3)

VSS(A3)

VPROT

HPROT

HSAFE

BSOIN

IBEAM

PROTON

Type Description

I/TTL Input for external line locked clock *)

Q Reference oscillator output, Crystal

I Reference oscillator input, Crystal

I/TTL Switching between internal (L) and external clock (H) *)

I/TTL Switching between normal operation (TEST=L) and test mode

(TEST=H: pins 4, 12, 13, 14, 15, 17, 49, 50, 63, 64 are additio-

nal test pins)

S Substrate pin, has to be connected to ground whenever a

power supply or signal is applied

I/TTL Reset input, active Low

I IÂ²C Bus clock

IQ IÂ²C Bus data

S Digital supply

S Digital ground

Q Control signal output for H driver stage (open drain)

Q/TTL Goes High when frequency of HSYNC is about 35kHz or more

Q/TTL Goes High when frequency of HSYNC is about 38kHz

Q/TTL Pulse width modulated control signal output

I/TTL V-sync input

I/TTL Switching between 1fH mode (L) and 2fH mode (H)

I HSYNC input (CLEXT=H: TTL; CLEXT=L: analog) *)

S Analog supply

S Analog ground

I Line flyback for H-delay compensation

S Analog supply

S Analog ground

Q Control signal output for East-West raster correction

Q Output of an IÂ²C Bus controlled DC voltage

Q Control signal output for DC coupled V-output stage

Q Like VD+

S Analog supply

S Analog ground

I Watching external V-output stage (input is the V-saw-tooth from

feedback resistor)

I Watching EHT (input is e.g. H-flyback)

I Watching B+ when frequency of HD has to be decreased

I Input for starting Black Switch-Off

I Input for a beam current dependent signal for stabilization of

width, height and H-phase

Q/TTL Protection on (goes High after response of H- or V-protection)

Micronas

4-5

2001-01-29

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