SDA9380-B21 Datasheet, PDF (52/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
Recommended operating conditions
Parameter
Symbol Min Nom Max Unit Remark
Input voltage when watching of
HSAFE is disabled
Input IBEAM
Low input voltage
Full range input voltage
Reference Voltage Pins
0
1.5
V
0
V
control bit RIBM=0
1.8
V
control bit RIBM=1
2.7
V
RIBM=0
2.7
V
RIBM=1
VREFH voltage
VREFN voltage
VREFC resistor to VREFN
Input Φ2
Low-level input voltage
V_IL
High-level input voltage
V_IH
Input HSYNC (CLEXT=Low)
1.568 1.6
0
27
1.632 V
V
kΩ
tolerance +- 2%
tolerance +- 2%
0
2.0V
0.7
V
V_DD
Input voltage range
Input voltage Low level
Input voltage High level
Pulse width (HSWMI=0)
V_HSpp
V_HSmin
V_HSmax
t_w
Pulse width (HSWMI=1)
t_w
*) High or Low level allowed, INCR = 6, see 5.2
Input HSYNC (CLEXT=High)
Low-level input voltage
V_IL
High-level input voltage
V_IH
Setup time
t_SU
2V
0V
1.5
3.0
0.8
1.7
0
2.0V
7
Hold time
t_H
6
V_DD
V_DD
4.5
µs
9.0
µs
4.5
µs
9.0
µs
see 5.2
see 5.2
see 5.2
*), FH1_2 = High
*), FH1_2 = Low
*), FH1_2 = High
*), FH1_2 = Low
0.8
V
V_DD
ns
ns
referred to rising
edge of CLKI
referred to rising
edge of CLKI
Micronas
8-44
2001-01-29