SDA9380-B21 Datasheet, PDF (40/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
System description
HSYNC
VSYNC
VD-
A
1
2
15 16 17 18 19 20 21 22 23 24 25
1 line
start of odd field
start of even field
VBL
(default:
BSE=0,
VBS=0,
VBE=0)
22 lines
R
GB
RGB
odd field
even field
VBL
(BSE=0,
VBS=2,
VBE=0)
2 lines
24 lines
R
GB
RGB
odd field
even field
VBL
(BSE=1,
RPP=1,
VBS=0,
VBE =1)
R
20 lines
GB
RGB
odd field
even field
Internal vertical blanking pulse VBL when JMP = 0 and number of lines per field = constant
b) Description of VBL when JMP= 1
Start of VBL = VBS lines before the first complete line of the next field
(def. value 0)
if BSE = 0
end of VBL = end of line (VBE + 29) (odd field)
width of VBL = (VBS + VBE + 29) lines (odd field)(def. value 29)
if BSE = 1
end of VBL = end of line (RPP + VBE + 25) (odd field)
width of VBL = (VBS + RPP + VBE + 25) lines (odd field)
Note! If JMP = 1 the number of lines between the last ref. pulse and the end of
VBL is defined by VBE in the range of 7 (VBE = 0) to 14 (VBE = 7).
Micronas
5-32
2001-01-29