SDA9380-B21 Datasheet, PDF (54/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
Recommended operating conditions
Parameter
Symbol Min Nom Max Unit Remark
Maximum input current during
clamping
I_i-clamp
100
Internal bias during clamping
Difference between black level of
internal and external signals at the
outputs
Delay difference of the three
channels
V_clamp
∆V_o
∆t_d
0.6
50
0
Fast Blanking Input FBL1 (RGB/YUV 1)
µA
V
mV
ns
1)
Input voltage no data insertion
V_i-n
Input voltage data insertion
V_i-y
0.9
Maximum input voltage
V_i-max
Difference between transit times for t_s - t_i
signal switching and signal insertion
0.5
V
V
3.3
V
10
ns
1)
Suppression of internal video signals
(insertion) or external video signals
(no insertion)
55
dB
f_i = 0 to 10 MHz, 1)
Fast Blanking/Contrast Reduction Input FBL2 (RGB2)
Maximum input voltage
V_i-max
Difference between transit times for t_s - t_i
signal switching and signal insertion
3.3
V
10
ns
1)
Suppression of internal video signals
(insertion) or external video signals
(no insertion)
55
dB
f_i = 0 to 10 MHz, 1)
Fast Blanking (Control bit COR1..COR0 = 00)
Input voltage no data insertion
V_i-n
0.5
V
Input voltage data insertion
V_i-y
0.9
V
Fast Blanking and Contrast Reduction (Control bit COR1..COR0 = 01...11)
Input voltage no contrast reduction V_icr-n
of internal RGB signals
Input voltage contrast reduction of V_icr-y
1.7
internal RGB signals
0.9
Contrast reduction (control bit
0
COR1..COR0)
Input voltage no data insertion
V_i-n
1.4
V
0.5
V
75
%
2
V
1.2
FBL2L = 0
FBL2L = 1
FBL2L = 0
FBL2L = 1
FBL2L = 0
FBL2L = 1
Micronas
8-46
2001-01-29