SDA9380-B21 Datasheet, PDF (21/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
System description
5.3 Reset modes
The circuit is only completely reset at power-on/off (timing diagram ref. 11.3). If the pin RESN has L-
level or during standby operation some parts of the circuit are not affected (timing diagram ref. 11.4):
HD output
H-protection
V-protection
IIC-Interface (SDA, SCL)
IIC-Register 01..1C
IIC-Register 00, 1D...30h
Status bit PONRES
VREFH
CPU
Power-On-Reset
High
inactive
inactive
tristate
set to default values
set to default values
set to 1²⁾
not affected
inactive
External Reset
(pin RESN=0)
active
active
active¹⁾
ready
set to default values
not affected
set to 1
not affected
inactive
Standby mode
(I²C bit STDBY=1)
active
active
active¹⁾
ready
set to default values
not affected
not affected
inactive
inactive
1)_{: inactive if HPROT < V2 (typ. 1.5V)}
2)_{: can only be read after Power-On-Reset is finished}
Note: Power-On-Reset state is deactivated after ca. 32768 cycles of the X1/X2 oscillator clock.
RESN=Low and standby state are deactivated after ca. 42 cycles of the CLL clock.
5.4 Frequency ranges
H
V
15.625 kHz
50 Hz
15.75 kHz
60 Hz
18.75 kHz*
60 Hz
31.25 kHz
50 Hz
100 Hz
31.5 kHz
60 Hz
70 Hz
120 Hz
33.75 kHz*
60 Hz
35 kHz*
66.7 Hz
38 kHz*
60 Hz
72 Hz
*) only with internal clock generation
n_L
625 I
525 I
625 I
625 NI / 1250 I
625 I
525 NI / 1050 I
449 NI
525 I
1125 I
525 NI
632 NI
525 NI
The allowed deviation of all input line frequencies is max. ±4.5%.
n_L : number of lines per frame
Micronas
5-13
2001-01-29