SDA9380-B21 Datasheet, PDF (14/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
Pin configuration
Pin No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
VREFH
VBLO
VREFN
VREFC
DCI
VDD(A4)
Y/R 0
U/G 0
V/B 0
VSS(A4)
R/Y 1
G/U 1
B/V 1
FBL1
FBL2
R2
G2
B2
VDD(MC)
ROUT
GOUT
BOUT
SCP
VSS(MC)
SVM
VDD(D)
VSS(D)
SSD
SWITCH
Type Description
IQ Reference voltage
Q/TTL Vertical blanking output
IQ Ground for VREFH
I Reference current input
I Dark current input for cut off and white level control
S Analog supply
I Luminance or R input
I U signal or G input
I V signal or B input
S Analog ground
I First R or Y input for insertion
I First G or U input for insertion
I First B or V input for insertion
I Fast blanking input for RGB1
I Fast blanking input for RGB2
I Second R input for insertion
I Second G input for insertion
I Second B input for insertion
S Analog supply for RGB output stage
Q R output
Q G output
Q B output
Q Blanking signal with H- and color burst component
(V-component selectable by I²C Bus)
S Analog ground for RGB output stage
Q Luminance output for scan velocity modulation circuit
S Digital supply
S Digital ground
I/TTL Disables softstart
Q/TTL Output of an I²C Bus controlled switch (register 00, bit SW)
*) The external clock mode can not be used with 18.75, 33.75kHz, 35kHz and 38kHz line frequency.
Micronas
4-6
2001-01-29