SDA9380-B21 Datasheet, PDF (26/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
System description
5.5.4 Detailed description
The Deflection control byte 0 includes the following bits:
VOFF STDBY MON SCLIIC RIBM CLEXTIIC HDDC
HDE
- VOFF:
Vertical off
0: normal vertical output due to control items
1: vertical saw-tooth is switched off,
vertical protection is disabled
- STDBY: Stand-by mode
0: normal operation
1: stand-by mode (all internal clocks are disabled)
- MON:
Monitor mode (GENMOD bit must be set to 0)
0: line frequency must be defined by INCR4..0 (register 1D)
1: automatic detection of line frequency
- SCLIIC: Select clock by IIC
0: select clock by pin CLEXT
1: select clock by IIC bit CLEXTIIC
- RIBM:
Input range of IBEAM
0: 0...2.7V
1: 1.8...2.7V
- CLEXTIIC:External clock selected by IIC (only effective if bit SCLIIC = 1)
0: internal clock selected by IIC
1: external clock selected by IIC
- HDDC:
HD duty cycle
0: duty cycle of output HD is 45%
1: duty cycle of output HD is 40%
- HDE:
HD enable
0: line is switched off (HD disabled, that is H-level)
If BSO1 =1 or BSO0 = 1, no switch-off is possible.
1: line is switched on (HD enabled)
Default value depends on pin SSD
SSD=Low: 0
SSD=High: 1
Micronas
5-18
2001-01-29