SDA9380-B21 Datasheet, PDF (53/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
Recommended operating conditions
Parameter
Symbol Min Nom Max Unit Remark
Input VSYNC
Pulse width high
100 ns
Pulse width high
200 ns
Pulse width high
1.5/fH
Input CLKI (external clock mode, CLEXT=high)
100/fH
100/fH
100/fH
FH1_2=1, NI=0
FH1_2=0, NI=0
NI=1
Input frequency
25
27
30
MHz
Quartz Oscillator Input / Output X1, X2
Crystal frequency
Crystal resonant impedance
External capacitance
YUV Inputs
24.576
40
15
MHz
Ω
pF
fundamental
crystal type, e.g.
Saronix
9922 520 00282
see 10
Y input voltage (black-to-white value) V_P-P
1
1.5
V
0.7
1.05 V
only Y0 input at
YLL = 1, or at
HDTV matrix
U input voltage (peak-to-peak value) V_P-P
1.33 2
V
0.7
1.05 V
U = - (B - Y),
at HDTV matrix
V input voltage (peak-to-peak value) V_P-P
1.05 1.6
V
0.7
1.05 V
V = - (R - Y),
at HDTV matrix
DC input current between clamping I_i
Input capacitance
C_i
Maximum input current during
clamping
I_i-clamp
100
100 nA
7
pF
µA
Internal bias during clamping at Y- V_clampY
0.6
V
input
Internal bias during clamping at UV- V_clampUV
1.1
V
inputs
RGB Inputs (RGB2, RGB/YUV1 if RGBEN1=1, YUV/RGB0 if RGBEN0=1)
Input voltage (black-to-white value) V_P-P
DC input current between clamping I_i
Input capacitance
C_i
0.7
1
V
100 nA
7
pF
Micronas
8-45
2001-01-29