SDA9380-B21 Datasheet, PDF (32/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
System description
The RGB control byte 1 includes the following bits:
BLUES SLBLKS BLCKS CTLPD WHITD
CATH2
CATH1
CATH0
- BLUES: Blue stretch
0: off
1: on
- SLBLKS: Slow Black stretch
0: short time constant
1: long time constant
- BLCKS: Black stretch
0: off
1: on
- CTLPD: Control loop disable
0: cut off and white level control loop are active
1: cut off and white level control loop are inactive (halt mode)
- WHITD: White level control loop disable
0: white level control loop is active
1: white level control loop is inactive (halt mode)
- CATH2..
CATH0: Cathode drive level (see 5.5.5 Explanation of some control items)
100: minmum level
..
011: +100% (maximum level)
The RGB control byte 2 includes the following bits:
BLUEB FBL2L
COR1
COR0 DELOFF SVMOFF
DEL1
DEL0
- BLUEB: Blue background
0: off
1: on
- FBL2L: FBL2 input switching level
0: high switching levels
1: low switching levels
Micronas
5-24
2001-01-29