SDA9380-B21 Datasheet, PDF (36/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
System description
The Status byte includes the following bits:
HPON VPON
CON
H38K
H35K
CLOW
-
PONRES
- HPON:
H-protection on
0: normal operation of the line output stage
1: upper threshold on input HPROT has been exceeded *)
- VPON:
V-protection on
0: normal operation of the vertical output stage
1: incorrect signal on input VPROT has been detected *)
- CON:
Coincidence not
0: H-coincidence detected
1: no H-coincidence detected
- H38K:
38 kHz line frequency
0: 38 kHz line frequency not detected
1: 38 kHz line frequency detected
- H35K:
35 kHz line frequency
0: 35 kHz line frequency not detected
1: 35 kHz line frequency detected
- CLOW:
Control loop out of window
0: all control loops inside of window
1: one of the control loop out of window
- PONRES:
Power On Reset
0: after bus master has read the status byte
1: after each detected reset
*) Also output PROTON (pin 35) goes High if HPON=1 or VPON=1.
Note!
PONRES is reset after this byte has been read.
Micronas
5-28
2001-01-29