SDA9380-B21 Datasheet, PDF (15/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
System description
5 System description
5.1 Functional description
5.1.1 Deflection controller
The main input signals are HSYNC with a frequency range of about 31 to 38kHz and VSYNC with
vertical frequencies of 50 to 120 Hz. When connecting pin FH1_2 with Low level a line frequency of
15 to 19kHz is suitable.
For displaying computer signals horizontal frequencies up to 38 kHz can be processed.
In the selectable Monitor mode the adaptation to the input frequency in the range of 31.25 to 38kHz
is done automatically. Two output pins (H35K and H38K) for controlling e.g. the supply voltage of the
line output stage indicate the frequency of HSYNC. When the H-frequency is increasing, these out-
puts are stable until the frequency of HSYNC appears on the output HD (see 11.1). In case of
decreasing H-frequency they are changed immediately to flag the new detected frequency but
change of the PLL frequency will be not allowed until the supply voltage of the H-output stage (B+)
is decreased. Pin HSAFE is used to watch B+.
The output signals control the horizontal as well as the vertical deflection stages and the East-West
raster correction circuit.
The H-output signal HD (open drain output) compensates the delays of the line output stage and its
phase can be modulated vertical frequent to remove horizontal distortions of vertical raster lines (V-
Bow, V-Angle). Time reference is the middle of the front and back edge of the line flyback pulse. A
positive HD pulse switches off the line output transistor. Maximal H-shift is about 2.25 µsec for
f_H=31kHz.
Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the aspect ratio of
the source signal.
The V-output saw-tooth signals VD- and VD+ controls a DC coupled output stage and can be dis-
abled. Suitable blanking signals are delivered by the IC.
The East-West output signal E/W is a vertical frequent parabola of 6th order, enabling an extreme
corner correction for super flat tubes. The common corner correction realised with coefficients of
fourth order, is separately adjustable for the upper and lower part of the screen.
The pulse width modulated horizontal frequent output signal PWM has two options. A vertical fre-
quent parabolic function or a constant pulse width in each line, selectable by I²C, is available. After
external integration the parabola may be used for vertical dynamic focusing rsp. the DC voltage for
adjustment of H-offset or rotation.
The output D/A delivers a variable DC signal and an I²C Bus controlled digital output is available for
general purpose.
The picture width and picture height compensation (PW/PH Comp) processes the beam current
dependent input signal IBEAM with effect to the outputs E/W and VD to keep width and height con-
stant and independent of brightness.
The alignment parameter AFC EHT Compensation enables to adjust the influence of the input sig-
nal IBEAM on the horizontal phase.
The selectable start up circuit controls the energy supply of the H-output stage during the receiver's
run up time by smooth decreasing the line output transistors switching frequency down to the nor-
mal operating value (softstart). HD starts with about 1.7 times the line frequency and converges
Micronas
5-7
2001-01-29