SDA9380-B21 Datasheet, PDF (3/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
DS¹ Date
Page
Changes compared to previous issue
24.03.99
46
DAC output D/A: DNL changed from +-0.5 LSB to +-1 LSB
29.03.99
22
IIC bus: ABLTCS1, 0 added
29.03.99
25
IIC bus: GAIN2 added, MODE changed
30.03.99
26
IIC bus: Peak drive limit, bit 3 added (hidden bit for Black stretch)
07.04.99
38
Input BSOIN: hysteresis added
12.04.99 22, 25, 15 IIC bus: ABLTCS1, 0 deleted, MODE default field frequent, Tdown
independent of MODE, default value for IIC reg. 27h set to -64
13.04.99
12
18.75kHz only possible with internal clock generation
19.04.99 45, 46 I²C bus specification completed
19.04.99
48
Hysteresis of H35K, H38K adjusted
19.04.99
19
PWMC data corrected in case of PWM output is used as switch output
20.04.99
53
Power-on reset thresholds added
20.04.99 17, 28, 29, default range of input IBEAM changed
39
20.04.99 17, 42 I²C bit RDCI added for switching of DCI input range
28.04.99 24, 50 Delay from SVM to RGB outputs reduced
28.04.99
49
Min. Bandwidth of RGB outputs specified
29.04.99
39
Pins for reference voltages VREFP, VREFL deleted
29.04.99 3,4,5,27,46 New output pin PROTON added
29.04.99 3,4,6,30,46 New output pin VBLO added
11.05.99 51, 52 Application information added
21.05.99 15, 43 Nominal saturation changed to -11
31.05.99
9
Delay of BG-pulse to HSYNC in internal clock mode changed
08.06.99 24, 40, 41 Differential input for RGB/YUV 1 removed
10.06.99
30
V-blanking component of SCP corresponds with internal blanking VBL
24.06.99 1, 2 RGB 1 input changed to RGB/YUV1, COR feature added
24.06.99
5
Test pins changed
24.06.99 12, 54, 55 Reset modes of IIC-Registers changed, POR delay changed to 32768
24.06.99 6,12,38,39, VREFP and VREFL removed, VREFH and VREFC changed
42, 46, 47,
48, 54, 55
24.06.99 40, 51, 52 External capacitances of the quartz oscillator changed to 15pF
24.06.99 40, 41 YUV and RGB inputs bias voltages added
24.06.99
43
Nominal value of saturation changed
24.06.99 46, 47 DAC outputs (E/W, D/A, VD+, VD-) changed
24.06.99
50
SVM output: black level added
24.06.99
54
POR levels changed
28.06.99 12, 58 Text RGB processing, diagrams black stretch and soft clipping added
29.06.99
8
Second paragraph changed (protection circuit)
30.06.99
29
Equations of Vertical EHT compensation changed
Micronas
ii
2001-01-29