SDA9380-B21 Datasheet, PDF (20/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
System description
Once an increment has been obtained, either from the PI-filter or the I²C-bus, it can be used to
operate the Digital Timing Oscillator. The DTO generates a saw-tooth with a frequency that is pro-
portional to the increment. The saw-tooth is converted into a sinusoidal clock signal by means of sin
ROM’s and D/A converters and applied to an analog PLL which multiplies the frequency by 4 (for
detailed explanation see pinning and I²C-bus description) and minimizes residual jitter. In this man-
ner the required line locked clock is provided to operate the other functional parts of the circuit. If no
HSYNC is applied to pin 18 the system holds its momentary frequency for 2040 lines and following
resets the PLL to its nominal frequency. The status bit CON indicates the lock state of the PLL.
The system also provides a stable HS-pulse for internal use. The phase between this internal pulse
and the external HSYNC is adjustable via I²C bus bits HPHASE. It can be shifted over the range of
one TV line.
An external clock (CLKI) can be provided by pin selection (CLEXT = H) or I²C control (SCLIIC = H,
CLEXTIIC = H). This is recommended when using the SDA 9380 with a scan rate conversion sys-
tem. The clock frequency has to be 864 · f_HSYNC. The external clock mode can not be used with
18.75, 33.75kHz, 35kHz and 38kHz line frequency. Therefore switching to external clock mode is
only possible when INCR = 6, but always allowed during operating without any danger for the H-out-
put stage.
The input signal at VSYNC is the vertical time reference. It has to pass a window avoiding too short
or long V-periods in the case of distorted or missing VSYNC pulses. The window allows a VSYNC
pulse only after a minimum number of lines from its predecessor and sets an artificial one after a
maximum number of lines. The window size is programmable by I²C-bus.
Values which influence shape and amplitude of the output signals are transmitted as reduced binary
values to the SDA 9380 via I²C bus. A CPU which is designed for speed reasons in a pipe line struc-
ture calculates in consideration of feedback signals (e.g. IBEAM) values which exactly represent the
output signals. These values control after D/A conversion the external deflection and raster correc-
tion circuits.
The CPU firmware is stored in an internal ROM.
Micronas
5-12
2001-01-29