SDA9380-B21 Datasheet, PDF (31/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
System description
The RGB control byte 0 includes the following bits:
IN2NOM IN1NOM CONTB
BD
VINP2E
FBL2E
VINP1E
FBL1E
- IN2NOM: Nominal saturation and contrast for video input 2
0: variable saturation and contrast for video input 2 (defined by reg. 24, 25)
1: fixed saturation and contrast for video input 2 (nominal values)
- IN1NOM: Nominal saturation and contrast for video input 1
0: variable saturation and contrast for video input 1 (defined by reg. 24, 25)
1: fixed saturation and contrast for video input 1 (nominal values)
- CONTB: Continuous blanking
0: off
1: on
- BD:
Blanking disable
0: horizontal and vertical blanking enabled
1: horizontal and vertical blanking disabled
- VINP2E, FBLE2, VINP1E, FBL1E: Selection of input signals (see table below)
VINP2E FBL2E VINP1E FBL1E
selected input signals
0
0
0
0
YUV/RGB 0
0
0
0
1
RGB/YUV 1 when FBL1=High else
YUV/RGB 0
0
0
1
X
RGB/YUV 1
0
1
0
0
RGB2 when FBL2=High else
YUV/RGB 0
RGB2 when FBL2=High
0
1
0
1
else RGB/YUV 1 when FBL1=High
else YUV/RGB 0
0
1
1
X
RGB2 when FBL2=High else
RGB/YUV 1
1
X
X
X
RGB 2
Micronas
5-23
2001-01-29