SDA9380-B21 Datasheet, PDF (56/72 Pages) Micronas – EDDC Enhanced Deflection Controller and RGB Processor

SDA 9380 - B21
Preliminary Data Sheet
Recommended operating conditions
Parameter
Symbol Min Nom Max Unit Remark
Saturation control (control bit B0...B5; subaddress 25h)
Saturation control range
52
Nominal saturation
B7...B2 = 110001
0
Contrast control (control bit B7...B0; subaddress 24h)
dB
63 steps
dB
Contrast control range
20
dB
255 steps
Nominal contrast
B7...B0 = 00000000
0
dB
Tracking between the three channels
over a control range of 10 dB
0.5
dB
Brightness control (control bit B7...B0; subaddress 23h)
Brightness control range
+- 0.75
Black level stretch (control bit BLCKS; subaddress 20h)
V
255 steps
Maximum black level shift
15
21
27
IRE
Level shift at 100% peak white
-1
0
1
IRE
Level shift at 50% peak white
-1
3
IRE
Level shift at 15% peak white
8
11
14
IRE
Peak drive limit (control byte peak drive limit, bits B7...B0; bit PDD)
Peak detector
Peak detector level (at the R, G or B
output at nominal white drive relative
to cut off)
IIC bus: peak drive limit B7...B4
minimum value (range -8)
maximum value (range +7)
Soft clipper
1.5
V
3.5
V
Starting level (relative to peak detek-
tors level)
IIC bus: peak drive limit B3, B2
10
11
00
01 (soft clipper off)
100
%
105
%
110
%
infinite
Micronas
8-48
2001-01-29