N25Q128A11B1241F Datasheet, PDF (92/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
several Dual Input Fast Program (DIFP) sequences each containing only a few bytes. See
Table 33.: AC Characteristics.
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is top) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress,
the Status Register and the Flag Status Register may be read to check if the internal modify
cycle is finished. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the
Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed.
Dual Input Fast Program cycle can be paused by mean of Program/Erase Suspend (PES)
instruction and resumed by mean of Program/Erase Resume (PER) instruction.
Figure 21. Dual Input Fast Program instruction sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction
24-bit address
DQ0
23 22 21
3210
DQ1
High Impedance
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
DQ0
64206420642064206420 6420
DATA IN 1 DATA IN 2 DATA IN 3
DATA IN 4
DATA IN 5
DATA IN 256
DQ1
7 5 3 1 75 31 75 3 175 3 17 5 3 1
MSB
MSB
MSB
MSB
MSB
7531
MSB
AI14229
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