N25Q128A11B1241F Datasheet, PDF (102/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
9.1.22
S
C
DQ0
DQ1
9.1.23
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit (or the Program/Erase controller bit of the Flag Status
Register) before sending a new instruction to the device. It is also possible to read the
Status Register continuously, as shown here.
Figure 30. Read Status Register instruction sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
High Impedance
Status register out
Status register out
76543210765432107
MSB
MSB
AI13734
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. After the write enable (WREN) instruction has been decoded and executed,
the device sets the write enable latch (WEL).
The write status register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on serial data input (DQ0).
The write status register (WRSR) instruction has no effect on b1 and b0 of the status
register.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed write status register cycle (whose duration is tow) is
initiated. While the write status register cycle is in progress, the status register may still be
read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1
during the self-timed write status register cycle, and is 0 when it is completed. When the
cycle is completed, the write enable latch (WEL) is reset.
The write status register (WRSR) instruction allows the user to change the values of the
block protect (BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated
as read-only, as defined in Table 3. The write status register (WRSR) instruction also allows
the user to set and reset the status register write disable (SRWD) bit in accordance with the
Write Protect (W/VPP) signal. The status register write disable (SRWD) bit and Write Protect
(W/VPP) signal allow the device to be put in the hardware protected mode (HPM). The write
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