N25Q128A11B1241F Datasheet, PDF (155/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Instructions
Figure 96. Read Volatile Configuration Register instruction sequence QIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
Volatile Configuration Register Out
DQ0
4040 4040404040
DQ1
5151 5151515151
DQ2
6262 626 2626262
DQ3
7 3 7 3 7 37 3 7 3 7 3 7 3
Quad_Read_VCR
9.3.22
Write Volatile Configuration Register
The Write Volatile Configuration register (WRVCR) instruction allows new values to be
written to the Volatile Configuration register. Before it can be accepted, a write enable
(WREN) instruction must previously have been executed. In case of Fast POR, the WREN
instruction is not required because a WREN instruction gets the device out from the Fast
POR state (See Section 11.1: Fast POR).
Apart form the parallelizing of the instruction code and the input data on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Volatile
Configuration Register (WRVCR) instruction of the Extended SPI protocol, please refer to
Section 9.1.31: Write Volatile Configuration Register for further details.
155/185