N25Q128A11B1241F Datasheet, PDF (124/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
9.2.13
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart
form the parallelizing of the instruction code and the output data on the two pins DQ0 and
DQ1, the instruction functionality is exactly the same as the Read Status Register (RDSR)
instruction of the Extended SPI protocol, please refer to Section 9.1.22: Read Status
Register (RDSR) for further details.
Figure 58. Read Status Register instruction sequence DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11
C
Instruction
Status Register Out
Byte
Byte
DQ0
6420 6420
9.2.14
DQ1
7531 7531
Dual_Read_SR
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. Apart form the parallelizing of the instruction code and the input data on the
two pins DQ0 and DQ1, the instruction functionality and the protection feature management
is exactly the same as the Write Status Register (WRSR) instruction of the Extended SPI
protocol, please refer to Section 9.1.23: Write status register (WRSR) for further details.
Figure 59. Write Status Register instruction sequence DIO-SPI
S
01234567
C
Status Register In
Instruction
Byte
DQ0
6420
DQ1
124/185
7531
Dual_Write_SR