N25Q128A11B1241F Datasheet, PDF (119/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Instructions
Figure 50. Dual Command Page Program instruction sequence DSP, A2h
S
1037 1039
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1036 1038
C
Instruction
24-Bit Address
Data Byte 1 Data Byte 2
Data Byte 256
DQ0
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 6 4 2 0
6420
DQ1
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 7 5 3 1
7531
Dual_Page_Program_A2h
Figure 51. Dual Command Page Program instruction sequence DSP, D2h
S
1037 1039
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1036 1038
C
Instruction
24-Bit Address
Data Byte 1 Data Byte 2
Data Byte 256
DQ0
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 6 4 2 0
6420
DQ1
9.2.7
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 7 5 3 1
7531
Dual_Page_Program_D2h
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code, address and input data on the two pins
DQ0 and DQ1, the instruction functionality (as well as the locking OTP method) is exactly
the same as the Program OTP (POTP) instruction of the Extended SPI protocol, please
refer to Section 9.1.16: Program OTP instruction (POTP) for further details.
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