N25Q128A11B1241F Datasheet, PDF (86/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
Figure 16. Quad Input/ Output Fast Read instruction sequence
S
Mode 3
C _{Mode 0}
DQ0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 23 24 25 26 27
Instruction
404040
IO switches from Input to Output
4040 4
DQ1
DQ2
Don’t Care
Don’t Care
515151
626262
5151 5
6 262 6
DQ3
9.1.8
737373
‘1’
7373 7
A23-16 A15-8 A7-0 Dummy (ex.: 10)
Byte 1 Byte 2
Quad_IO_Fast_Read
Read OTP (ROTP)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each
bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on Serial Data output (DQ1).
Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock
(C). The instruction sequence is shown in Figure 17.
The address is automatically incremented to the next higher address after each byte of data
is shifted out.
There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the
Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read. All other
bytes outside the OTP area are “Don’t Care.”
The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read OTP (ROTP)
instruction issued while an Erase, Program or Write cycle is in progress, is rejected without
having any effect on the cycle that is in progress.
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