N25Q128A11B1241F Datasheet, PDF (117/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Instructions
Figure 46. Read OTP instruction and data-out sequence DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
C
DQ0
Instruction
24-Bit Address
22 20 18 16 14 12 10 8 6 4 2 0
Dummy cycles
Data Out 1
6420
Data Out n
6420
DQ1
9.2.4
23 21 19 17 15 13 11 9 7 5 3 1
7531
MSB
7531
MSB
Dual_Read_OTP
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit.
Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Enable (WREN) instruction of the
Extended SPI protocol.
Figure 47. Write Enable instruction sequence DIO-SPI
S
01234
C
Instruction
DQ0
9.2.5
DQ1
Dual_Write_Enable
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.
Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Disable (WRDI) instruction of the
Extended SPI protocol, please refer to Section 9.1.10: Write Disable (WRDI) for further
details.
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