N25Q128A11B1241F Datasheet, PDF (153/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Instructions
Figure 94. Read NV Configuration Register instruction sequence QIO-SPI
S
012345
C
Instruction
Nonvolatile Configuration
Register Out
DQ0
4 0 12 8
DQ1
5 1 13 9
DQ2
6 2 14 10
9.3.20
DQ3
7 3 15 11
LS Byte MS Byte
Quad_Read_NVCR
Write NV Configuration Register
The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to
be written to the Non Volatile Configuration register. Before it can be accepted, a write
enable (WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code and the input data on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Non
Volatile Configuration Register (WRNVCR) instruction of the Extended SPI protocol, please
refer to Section 9.1.29: Write NV Configuration Register for further details.
153/185