N25Q128A11B1241F Datasheet, PDF (107/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Figure 35. Clear Flag Status Register instruction sequence
S
012345678
C
Instruction
Instructions
9.1.28
S
C
DQ0
DQ1
9.1.29
DQ0
DQ1
High Impedance
MSB
Clear_Flag_SR
Read NV Configuration Register
The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile
Configuration Register to be read.
Figure 36. Read NV Configuration Register instruction sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
High Impedance
NVCR Out
NVCR Out
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
LS Byte
MS Byte
Read_NVCR
Write NV Configuration Register
The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to
be written to the Non Volatile Configuration register. Before it can be accepted, a write
enable (WREN) instruction must previously have been executed. After the write enable
(WREN) instruction has been decoded and executed, the device sets the write enable latch
(WEL).
The Write Non Volatile Configuration register (WRNVCR) instruction is entered by driving
Chip Select (S) Low, followed by the instruction code and the data bytes on serial data input
(DQ0).
Chip Select (S) must be driven High after the 16th bit of the data bytes has been latched in.
If not, the Write Non Volatile Configuration register (WRNVCR) instruction is not executed.
107/185