N25Q128A11B1241F Datasheet, PDF (164/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

XIP Operations
N25Q128 - 1.8 V
10.2
Note:
Enter XIP mode by setting the Volatile Configuration Register
To use the Volatile Configuration Register method to enter XIP mode, it is necessary to write
a 0 to bit 3 of the Volatile Configuration Register to make the device ready to enter XIP
mode (2). This instruction doesn't permit to enter XIP state directly: a Fast Read instruction
(either Single, Dual or Quad) is needed once to start the XIP Reading.
After the Fast Read instruction (Single, Dual or Quad) the XIP confirmation bit must be set
to 0. (first bit on DQ0 during the first dummy cycle after the address has been received),
Then after the next de-select and select cycle (S pin set to 1 and then to 0) the memory
codify the first 3 bytes received on the input pin(s) directly as an address, without any
instruction code, and after the dummy clock cycles (configurable) directly outputs the data.
For example to enable the XIP (without enter) with six dummy clock cycles, the pattern in
Table 26.: VCR XIP bits setting example must be issued, and after that it is possible to enter,
for example, in XIP mode from extended SPI read mode by mean of Quad Input Output Fast
Read instruction, as described in Table 26.: VCR XIP bits setting example.
For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not
necessary to set the Volatile Configuration Register bit 3 to enter in XIP mode: it is possible
to enter directly in XIP mode by setting XIP Confirmation bit to 1 during the first dummy
clock cycle after a fast read instruction. See Section 16: Ordering information.
Table 26. VCR XIP bits setting example
81h (WRVCR opcode)
+ 0110
6 dummy
cycles
0
Ready for
XIP
000
Reserved
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