N25Q128A11B1241F Datasheet, PDF (19/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
3
SPI Modes
SPI Modes
These devices can be driven by a micro controller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in standby mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. Bus master and memory devices on the SPI bus
R
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDO
SDI
SCK
SPI Bus Master
V_SS
V_CC
C
V_CC
DQ1 DQ0
V_SS
C
V_CC
DQ1 DQ0
V_SS
C
V_CC
DQ1 DQ0
V_SS
CS3 CS2 CS1
R
SPI memory _R
device
S
W HOLD
SPI memory _R
device
SPI memory
device
S
W HOLD
S
W HOLD
AI13725b
Shown here is an example of three devices working in Extended SPI protocol for simplicity
connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one
device drives the serial data output (DQ1) line at a time; the other devices are high
impedance. Resistors R ensures that the N25Q128 is not selected if the bus master leaves
the S line in the high impedance state. As the bus master may enter a state where all
inputs/outputs are in high impedance at the same time (for example, when the bus master is
reset), the clock line (C) must be connected to an external pull-down resistor so that, when
all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled
Low. This ensures that S and C do not become High at the same time, and so that the t_SHCH
requirement is met. The typical value of R is 100 kΩ, assuming that the time constant R*C_p
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