N25Q128A11B1241F Datasheet, PDF (106/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
9.1.26
S
C
DQ0
DQ1
9.1.27
Table 22. Lock Register in⁽¹⁾
Sector
Bit
Value
All sectors
b7-b2
b1
b0
‘0’
Sector Lock Down bit value (refer to Table 21)
Sector Write Lock bit value (refer to Table 21)
1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes.
Read Flag Status Register
The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be
read. The Status Register may be read at any time, even while a Program, Erase. When one
of these cycles is in progress, it is recommended to check the P/E Controller bit (Not WIP)
bit before sending a new instruction to the device. It is also possible to read the Flag
Register continuously, as shown here.
Figure 34. Read Flag Status Register instruction sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
High Impedance
Flag Status Register Out
Flag Status Register Out
76543210765432107
MSB
MSB
Read_Flag_SR
Clear Flag Status Register
The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits
(Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to
set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit
will be unchanged after this command is executed.
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