N25Q128A11B1241F Datasheet, PDF (84/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
Figure 14. Dual I/O Fast Read instruction sequence
S
Mode 3
C _{Mode 0}
DQ0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Instruction
642064206420
DQ1
S
C
DQ0
DQ1
9.1.6
7531 7531 7531
Address
Dummy Cycles
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
IO switches from Input to Output
6420642064206420 6
75317531 75317531 7
Byte 1
Byte 2
Byte 3
Byte 4
Dual_IO_Fast_Read
Quad Output Fast Read
The Quad Output Fast Read (QOFR) instruction is very similar to the Dual Output Fast
Read (DOFR) instruction, except that the data are shifted out on four pins (pin DQ0, pin
DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 (1) instead of only two. Outputting the data on
four pins instead of one doubles the data transfer bandwidth compared to the Dual Output
Fast Read (DOFR) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the Quad
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte,
each bit being latched-in during the rising edge of Serial Clock (C). Then the memory
contents, at that address, are shifted out on pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin
HOLD/DQ3 (1) at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 15.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on pin DQ0, pin DQ1, pin
W/VPP/DQ2 and pin HOLD/DQ3 (1). The whole memory can, therefore, be read with a
single Quad Output Fast Read (QOFR) instruction.
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
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