N25Q128A11B1241F Datasheet, PDF (144/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
9.3.10
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and
DQ3, the instruction functionality is exactly the same as the Bulk Erase (BE) instruction of
the Extended SPI protocol, please refer to Section 9.1.19: Bulk Erase (BE) for further
details.
Figure 85. Bulk Erase instruction sequence QIO-SPI
S
C
DQ0
01
Instruction
DQ1
DQ2
DQ3
9.3.11
Quad_Bulk_Erase
Program/Erase Suspend
The Program/Erase Suspend instruction allows the controller to interrupt a Program or an
Erase instruction, in particular: Sector Erase and Quad Command Page Program can be
suspended and erased while that Subsector Erase, Bulk Erase, Write Non Volatile
Configuration register and Program OTP can not be suspended.
Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and
DQ3, the instruction functionality is exactly the same as the Program/Erase Suspend (PES)
instruction of the Extended SPI protocol, please refer to Section 9.1.20: Program/Erase
Suspend for further details.
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