N25Q128A11B1241F Datasheet, PDF (108/185 Pages) Micron Technology – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
S
C
DQ0
DQ1
9.1.30
As soon as Chip Select (S) is driven High, the self-timed write NV configuration register
cycle (whose duration is tnvcr) is initiated.
While the Write Non Volatile Configuration register cycle is in progress, it is possible to
monitor the end of the process by polling status Register write in progress (WIP) bit or the
Flag Status Register Program/Erase Controller bit. The write in progress (WIP) bit is 1
during the self-timed Write Non Volatile Configuration register cycle, and is 0 when it is
completed. When the cycle is completed, the write enable latch (WEL) is reset.
The Write Non Volatile Configuration register (WRNVCR) instruction allows the user to
change the values of all the Non Volatile Configuration Register bits, described in Table 4.:
Non-Volatile Configuration Register.
The Write Non Volatile Configuration Register impacts the memory behavior only after the
next power on sequence.
Figure 37. Write NV Configuration Register instruction sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Instruction
High Impedance
NVCR In
Byte
Byte
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
LS Byte
MS Byte
Write_NVCR
Read Volatile Configuration Register
The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile
Configuration Register to be read. See Table 6.: Volatile Configuration Register.
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