MT40A1G4RH-083E Datasheet, PDF(92/365 Page) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

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MT40A1G4RH-083E Datasheet, PDF (92/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

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4Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

Table 32: MPR Readout â Parallel Format (Continued)

Parallel

UI0

UI1

UI2

UI3

UI4

UI5

UI6

UI7

DQ5

1

1

1

1

1

1

1

1

DQ6

1

1

1

1

1

1

1

1

DQ7

1

1

1

1

1

1

1

1

DQ8

0

0

0

0

0

0

0

0

DQ9

1

1

1

1

1

1

1

1

DQ10

1

1

1

1

1

1

1

1

DQ11

1

1

1

1

1

1

1

1

DQ12

1

1

1

1

1

1

1

1

DQ13

1

1

1

1

1

1

1

1

DQ14

1

1

1

1

1

1

1

1

DQ15

1

1

1

1

1

1

1

1

MPR Readout Staggered Format

Staggered format of data return is defined as the staggering of the MPR data across the

lanes. In this mode, an RD/RDA command is issued to a specific data pattern location

and then the data is returned on the DQ from each of the different data pattern loca-

tions. For the x4 configuration, an RD/RDA to data pattern location 0 will result in data

from location 0 being driven on DQ0, data from location 1 being driven on DQ1, data

from location 2 being driven on DQ2, and so on, as shown below. Similarly, an RD/RDA

command to data pattern location 1 will result in data from location 1 being driven on

DQ0, data from location 2 being driven on DQ1, data from location 3 being driven on

DQ2, and so on. Examples of different starting locations are also shown.

Table 33: MPR Readout Staggered Format, x4

x4 READ MPR0 Command

Stagger

UI[7:0]

DQ0

MPR0

DQ1

MPR1

DQ2

MPR2

DQ3

MPR3

x4 READ MPR1 Command x4 READ MPR2 Command x4 READ MPR3 Command

Stagger

UI[7:0]

Stagger

UI[7:0]

Stagger

UI[7:0]

DQ0

MPR1

DQ0

MPR2

DQ0

MPR3

DQ1

MPR2

DQ1

MPR3

DQ1

MPR0

DQ2

MPR3

DQ2

MPR0

DQ2

MPR1

DQ3

MPR0

DQ3

MPR1

DQ3

MPR2

It is expected that the DRAM can respond to back-to-back RD/RDA commands to the

MPR for all DDR4 frequencies so that a sequence (such as the one that follows) can be

created on the data bus with no bubbles or clocks between read data. In this case, the

system memory controller issues a sequence of RD(MPR0), RD(MPR1), RD(MPR2),

RD(MPR3), RD(MPR0), RD(MPR1), RD(MPR2), and RD(MPR3).

Table 34: MPR Readout Staggered Format, x4 â Consecutive READs

Stagger

DQ0

DQ1

UI[7:0]

MPR0

MPR1

UI[15:8]

MPR1

MPR2

UI[23:16]

MPR2

MPR3

UI[31:24]

MPR3

MPR0

UI[39:32]

MPR0

MPR1

UI[47:40]

MPR1

MPR2

UI[55:48]

MPR2

MPR3

UI[63:56]

MPR3

MPR0

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4gb_ddr4_dram.pdf - Rev. G 1/17 EN

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