MT40A1G4RH-083E Datasheet, PDF (219/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 161: Write Timing Definition
T0
T1
T2
T7
T8
T9
T10
T11
T12
T13
CK_c
CK_t
Command³ WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
WL = AL + CWL
Address⁴
Bank,
Col n
t_{DQSS (MIN)}
DQS_t, DQS_c
DQ²
t_DQSS t_DSH
t_WPRE(1nCK)
t_DSH
t_DSH
t_DSH
t_WPSTaa
t_DQSL
t_{DQSH (MIN)}
t_DSS
t_DQSH
D_IN
n
t_DQSL t_DQSH t_DQSL t_DQSH
t_DSS
D_IN
n+ 2
t_DSS
D_IN
n+ 3
D_IN
n+ 4
t_{DQSL tDQSH}
t_{DQSL (MIN)}
t_DSS
t_DSS
D_IN
n+ 6
D_IN
n+ 7
T14
DES
t_{DQSS (nominal)}
DQS_t, DQS_c
DQ²
t_WPRE(1nCK)
t_DSH
t_DSH
t_DSH
t_DSH
t_{WPST (MIN)}
t_{DQSH (MIN)}
t_DQSL
t_DSS
t_DQSH
t_DQSL t_DQSH
t_DSS
t_DQSL t_DQSH
t_DSS
t_DQSL
t_DSS
t_DQSH
t_{DQSL (MIN)}
t_DSS
D_IN
D_IN
D_IN
D_IN
D_IN
D_IN
n
n+ 2 n+ 3 n+ 4
n+ 6
n+ 7
t_{DQSS (MAX)}
DQS_t, DQS_c
DQ²
t_DQSS
t_WPRE(1nCK)
t_DSH
t_DSH
t_DSH
t_DSH
t_{WPST (MIN)}
t_DQSL t_DQSH t_DQSL t_DQSH t_DQSL t_DQSH t_DQSL t_DQSH
t_{DQSH (MIN)}
t_{DQSL (MIN)}
t_DSS
D_IN
n
t_DSS
D_IN
n+ 2
t_DSS
D_IN
n+ 3
D_IN
n+ 4
t_DSS
D_IN
n+ 6
t_DSS
D_IN
n+ 7
DM_n
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, WL = 9 (AL = 0, CWL = 9).
2. D_INn = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. ^tDQSS must be met at each rising clock edge.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
219
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.