MT40A1G4RH-083E Datasheet, PDF (154/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Power-Down Mode
Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW (along with a DESE-
LECT command). CKE is not allowed to go LOW when the following operations are in
progress: MRS command, MPR operations, ZQCAL operations, DLL locking, or READ/
WRITE operations. CKE is allowed to go LOW while any other operations, such as ROW
ACTIVATION, PRECHARGE or auto precharge, or REFRESH, are in progress, but the
power-down I_DD specification will not be applied until those operations are complete.
The timing diagrams that follow illustrate power-down entry and exit.
For the fastest power-down exit timing, the DLL should be in a locked state when pow-
er-down is entered. If the DLL is not locked during power-down entry, the DLL must be
reset after exiting power-down mode for proper READ operation and synchronous ODT
operation. DRAM design provides all AC and DC timing and voltage specification as
well as proper DLL operation with any CKE intensive operations as long as the control-
ler complies with DRAM specifications.
During power-down, if all banks are closed after any in-progress commands are com-
pleted, the device will be in precharge power-down mode; if any bank is open after in-
progress commands are completed, the device will be in active power-down mode.
Entering power-down deactivates the input and output buffers, excluding CK, CKE, and
RESET_n. In power-down mode, DRAM ODT input buffer deactivation is based on MRx
bit Y. If it is configured to 0b, the ODT input buffer remains on and the ODT input signal
must be at valid logic level. If it is configured to 1b, the ODT input buffer is deactivated
and the DRAM ODT input signal may be floating and the device does not provide
R_TT(NOM) termination. Note that the device continues to provide R_TT(Park) termination if
it is enabled in the mode register MRa bit B. To protect internal delay on the CKE line to
block the input signals, multiple DES commands are needed during the CKE switch off
and on cycle(s); this timing period is defined as ^tCPDED. CKE LOW will result in deacti-
vation of command and address receivers after ^tCPDED has expired.
Table 52: Power-Down Entry Definitions
DRAM Status
DLL
Active
On
(a bank or more open)
Precharged
On
(all banks precharged)
Power-
Down Exit Relevant Parameters
Fast
t_{XP to any valid command.}
Fast
t_{XP to any valid command.}
The DLL is kept enabled during precharge power-down or active power-down. In pow-
er-down mode, CKE is LOW, RESET_n is HIGH, and a stable clock signal must be main-
tained at the inputs of the device. ODT should be in a valid state, but all other input sig-
nals are "Don't Care." (If RESET_n goes LOW during power-down, the device will be out
of power-down mode and in the reset state.) CKE LOW must be maintained until ^tCKE
has been satisfied. Power-down duration is limited by 9 × ^tREFI.
The power-down state is synchronously exited when CKE is registered HIGH (along
with DES command). CKE HIGH must be maintained until ^tCKE has been satisfied. The
ODT input signal must be at a valid level when the device exits from power-down mode,
independent of MRx bit Y if R_TT(NOM) is enabled in the mode register. If R_TT(NOM) is disa-
bled, the ODT input signal may remain floating. A valid, executable command can be
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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