MT40A1G4RH-083E Datasheet, PDF (235/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 182: WRITE (BC4) OTF to READ (BC4) OTF with 1^tCK Preamble in Different Bank Group
T0
CK_c
CK_t
Command WRITE
Bank Group
BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T24
T25
T26
T27
T28
T29
DES
DES
DES
DES
t_WPRE
DES
DES
DES
4 Clocks
t_WPST
DES
DES
READ
DES
DES
t_{WTR_S = 2}
BGb
Bank
Col b
DES
DES
DES
t_RPRE
DES
DES
t_RPST
WL = AL + CWL = 9
DI DI DI DI
n n+1 n+2 n+3
RL = AL + CL = 11
DI DI DI DI
b b+1 b+2 b+3
Time Break
Transitioning Data
Don’t Care
Notes:
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1^tCK, WRITE preamble =
1^tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and
READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (^tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T13.
Figure 183: WRITE (BC4) OTF to READ (BC4) OTF with 1^tCK Preamble in Same Bank Group
T0
CK_c
CK_t
Command WRITE
Bank Group
BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T26
T27
T28
T29
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
4 Clocks
t_{WTR_L = 4}
BGa
t_WPRE
t_WPST
Bank
Col b
t_RPRE
WL = AL + CWL = 9
DI DI DI DI
n n+1 n+2 n+3
RL = AL + CL = 11
DI DI DI
b b+1 b+2
Time Break
Transitioning Data
Don’t Care
Notes:
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1^tCK, WRITE preamble =
1^tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and
READ command at T17.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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