MT40A1G4RH-083E Datasheet, PDF (232/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (^tWR) and write timing parameter (^tWTR) are referenced from
the first rising clock edge after the last write data shown at T15.
Figure 178: WRITE (BL8) to WRITE (BC4) OTF with 1^tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK_c
CK_t
Command WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Bank Group
BGa
Address
t_{CCD_S = 4}
BGb
4 Clocks
Address
Bank
Col n
DQS_t,
DQS_c
DQ
WL = AL + CWL = 9
Bank
Col b
t_WPRE
t_WPST
DI DI DI DI DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3
WL = AL + CWL = 9
T18
T19
DES
DES
t_WR
t_WTR
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1^tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.
6. The write recovery time (^tWR) and write timing parameter (^tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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