MT40A1G4RH-083E Datasheet, PDF (324/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Table 145: I_DD7 Measurement – Loop Pattern¹
Data³
0
0
ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0
–
1
RDA 0 1 1 0 1 0 0 0 0 0 1 0 0 0
2
D 10000000000000
–
3
D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0
–
...
Repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary
1
nRRD
ACT 0 0 0 0 0 0 1 1 0 0 0 0 0 0
–
nRRD+1
RDA 0 1 1 0 1 0 1 1 0 0 1 0 0 0
...
Repeat pattern 2...3 until 2 × nRRD - 1, if nRRD > 4. Truncate if necessary
2
2 × nRRD
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
3 × nRRD
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
4 × nRRD
Repeat pattern 2...3 until nFAW - 1, if nFAW > 4 × nRRD. Truncate if necessary
5
nFAW
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
6
nFAW + nRRD
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
7 nFAW + 2 × nRRD
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
8 nFAW + 3 × nRRD
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
9 nFAW + 4 × nRRD
Repeat sub-loop 4
10
2 × nFAW
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead
11 2 × nFAW + nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead
12 2 × nFAW + 2 ×
nRRD
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead
13 2 × nFAW + 3 ×
nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead
14 2 × nFAW + 4 ×
nRRD
Repeat sub-loop 4
15
3 × nFAW
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead
16 3 × nFAW + nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead
17 3 × nFAW + 2 ×
nRRD
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead
18 3 × nFAW + 3 ×
nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead
19 3 × nFAW + 4 ×
nRRD
Repeat sub-loop 4
20
4 × nFAW
Repeat pattern 2...3 until nRC - 1, if nRC > 4 × nFAW. Truncate if necessary
Notes:
1. DQS_t, DQS_c are V_DDQ.
2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are V_DDQ except when burst sequence drives each DQ signal by a READ com-
mand.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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