MT40A1G4RH-083E Datasheet, PDF (217/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
2. DI n (or b) = data-in from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T3 and T7.
5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. Enabling CAL mode does not impact ODT control timings. The same timing relationship
relative to the command/address bus as when CAL is disabled should be maintained.
Figure 160: Consecutive READ (BL8) with CAL (4^tCK) and 1^tCK Preamble in Different Bank Group
T0
CK_c
CK_t
Command
w/o CS_n
CS_n
Bank Group
Address
T1
T2
T3
T4
T5
T6
T7
T8
T14
T15
T16
T18
T19
T21
T22
T23
T24
t_{CAL = 4}
t_{CAL = 4}
DES
DES
READ
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_{CCD_S = 4}
BGa
BGb
Address
DQS_t,
DQS_c
DQ
Bank
Col n
RL = 11
Bank
Col b
t_RPRE
t_RPST
DI DI DI DI DI DI DI DI DI DI DI DI
n n+1 n+2 n+5 n+6 n+7 b b+1 b+2 b+5 b+6 b+7
RL = 11
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1^tCK.
2. DI n (or b) = data-in from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T3 and T8.
5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. Enabling CAL mode does not impact ODT control timings. The same timing relationship
relative to the command/address bus as when CAL is disabled should be maintained.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
217
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