MT40A1G4RH-083E Datasheet, PDF (89/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
or 100. After power-up, the content of MPR Page 0 has the default values, which are de-
fined in Table 30. MPR page 0 can be rewritten via an MPR WRITE command. The de-
vice maintains the default values unless it is rewritten by the DRAM controller. If the
DRAM controller does overwrite the default values (Page 0 only), the device will main-
tain the new values unless re-initialized or there is power loss.
Timing in MPR mode:
• Reads (back-to-back) from Page 0 may use ^tCCD_S or ^tCCD_L timing between READ
commands
• Reads (back-to-back) from Pages 1, 2, or 3 may not use ^tCCD_S timing between READ
commands; ^tCCD_L must be used for timing between READ commands
The following steps are required to use the MPR to read out the contents of a mode reg-
ister (MPR Page x, MPRy).
1. The DLL must be locked if enabled.
2. Precharge all; wait until ^tRP is satisfied.
3. MRS command to MR3[2] = 1 (Enable MPR data flow), MR3[12:11] = MPR read for-
mat, and MR3[1:0] MPR page.
a. MR3[12:11] MPR read format:
1. 00 = Serial read format
2. 01 = Parallel read format
3. 10 = staggered read format
4. 11 = RFU
b. MR3[1:0] MPR page:
1. 00 = MPR Page 0
2. 01 = MPR Page 1
3. 10 = MPR Page 2
4. 11 = MPR Page 3
4. ^tMRD and ^tMOD must be satisfied.
5. Redirect all subsequent READ commands to specific MPRx location.
6. Issue RD or RDA command.
a. BA1 and BA0 indicate MPRx location:
1. 00 = MPR0
2. 01 = MPR1
3. 10 = MPR2
4. 11 = MPR3
b. A12/BC = 0 or 1; BL8 or BC4 fixed-only, BC4 OTF not supported.
1. If BL = 8 and MR0 A[1:0] = 01, A12/BC must be set to 1 during MPR
READ commands.
c. A2 = burst-type dependant:
1. BL8: A2 = 0 with burst order fixed at 0, 1, 2, 3, 4, 5, 6, 7
2. BL8: A2 = 1 not allowed
3. BC4: A2 = 0 with burst order fixed at 0, 1, 2, 3, T, T, T, T
4. BC4: A2 = 1 with burst order fixed at 4, 5, 6, 7, T, T, T, T
d. A[1:0] = 00, data burst is fixed nibble start at 00.
e. Remaining address inputs, including A10, and BG1 and BG0 are "Don’t
Care."
7. After RL = AL + CL, DRAM bursts data from MPRx location; MPR readout format
determined by MR3[A12,11,1,0].
8. Steps 5 through 7 may be repeated to read additional MPRx locations.
9. After the last MPRx READ burst, ^tMPRR must be satisfied prior to exiting.
10. Issue MRS command to exit MPR mode; MR3[2] = 0.
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