MT40A1G4RH-083E Datasheet, PDF (276/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Figure 215: CT Type-C Input Slew Rate Definition
V_{IH(AC)_TENmin}
V_{IH(DC)_TENmin}
V_{IL(DC)_TENmin}
V_{IL(AC)_TENmin}
t_{F_TEN}
t_{R_TEN}
Table 97: CT Type-D Input Levels
Parameter
CTipD AC input high voltage
CTipD DC input high voltage
CTipD DC input low voltage
CTipD AC input low voltage
Rising time
RESET pulse width - after power-up
RESET pulse width - during power-up
Symbol
V_{IH(AC)_CTipD}
V_{IH(DC)_CTipD}
V_{IL(DC)_CTipD}
V_{IL(AC)_CTipD}
t_{R_RESET}
t_{PW_RESET_S}
t_{PW_RESET_L}
Min
0.8 × V_DD
0.7 × V_DD
V_SS
V_SS
–
1
200
Max
V_DD
V_DD
0.3 × V_DD
0.2 × V_DD
1
–
–
Unit
V
V
V
V
μs
μs
μs
Note
4
2
1
5
3
Notes:
1. After RESET_n is registered LOW, the RESET_n level must be maintained below V_{IL(DC)_RE-}
SET ^{during tPW_RESET, otherwise, the DRAM may not be reset.}
2. After RESET_n is registered HIGH, the RESET_n level must be maintained above
V_{IH(DC)_RESET}, otherwise, operation will be uncertain until it is reset by asserting RESET_n
signal LOW.
3. Slope reversal (ring-back) during this level transition from LOW to HIGH should be miti-
gated as much as possible.
4. Overshoot should not exceed the V_IN values in the Absolute Maximum Ratings table.
5. Undershoot should not exceed the V_IN values in the Absolute Maximum Ratings table.
6. CT Type-D inputs: RESET_n; same requirements as in normal mode.
Figure 216: CT Type-D Input Slew Rate Definition
V_{IH(AC)_RESETmin}
V_{IH(DC)_RESETmin}
t_{PW_RESET}
V_{IL(DC)_RESETmax}
V_{IL(AC)_RESETmax}
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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t_{R_RESET}
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