MT40A1G4RH-083E Datasheet, PDF (6/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Features
V_REFDQ Increment and Decrement Timing .................................................................................................. 119
V_REFDQ Target Settings ............................................................................................................................... 123
Connectivity Test Mode ................................................................................................................................. 125
Pin Mapping ............................................................................................................................................. 125
Minimum Terms Definition for Logic Equations ......................................................................................... 126
Logic Equations for a x4 Device, When Supported ....................................................................................... 126
Logic Equations for a x8 Device, When Supported ....................................................................................... 127
Logic Equations for a x16 Device ................................................................................................................ 127
CT Input Timing Requirements .................................................................................................................. 127
Post Package Repair ....................................................................................................................................... 129
Post Package Repair ................................................................................................................................... 129
Hard Post Package Repair .......................................................................................................................... 130
hPPR Row Repair - Entry ........................................................................................................................ 130
hPPR Row Repair – WRA Initiated (REF Commands Allowed) .................................................................. 130
hPPR Row Repair – WR Initiated (REF Commands NOT Allowed) ............................................................. 132
sPPR Row Repair ....................................................................................................................................... 133
hPPR/sPPR Support Identifier .................................................................................................................... 136
Excessive Row Activation ............................................................................................................................... 138
ACTIVATE Command .................................................................................................................................... 138
PRECHARGE Command ................................................................................................................................ 139
REFRESH Command ..................................................................................................................................... 140
Temperature-Controlled Refresh Mode .......................................................................................................... 142
TCR Mode – Normal Temperature Range .................................................................................................... 142
TCR Mode – Extended Temperature Range ................................................................................................. 142
Fine Granularity Refresh Mode ....................................................................................................................... 144
Mode Register and Command Truth Table .................................................................................................. 144
t_{REFI and} t_{RFC Parameters ........................................................................................................................ 144}
Changing Refresh Rate ............................................................................................................................... 147
Usage with TCR Mode ................................................................................................................................ 147
Self Refresh Entry and Exit ......................................................................................................................... 147
SELF REFRESH Operation .............................................................................................................................. 149
Self Refresh Abort ...................................................................................................................................... 151
Self Refresh Exit with NOP Command ......................................................................................................... 152
Power-Down Mode ........................................................................................................................................ 154
Power-Down Clarifications – Case 1 ........................................................................................................... 159
Power-Down Entry, Exit Timing with CAL ................................................................................................... 160
ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 162
CRC Write Data Feature ................................................................................................................................. 164
CRC Write Data ......................................................................................................................................... 164
WRITE CRC DATA Operation ...................................................................................................................... 164
DBI_n and CRC Both Enabled .................................................................................................................... 165
DM_n and CRC Both Enabled .................................................................................................................... 165
DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 165
CRC and Write Preamble Restrictions ......................................................................................................... 165
CRC Simultaneous Operation Restrictions .................................................................................................. 165
CRC Polynomial ........................................................................................................................................ 165
CRC Combinatorial Logic Equations .......................................................................................................... 166
Burst Ordering for BL8 ............................................................................................................................... 167
CRC Data Bit Mapping ............................................................................................................................... 167
CRC Enabled With BC4 .............................................................................................................................. 168
CRC with BC4 Data Bit Mapping ................................................................................................................ 168
CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 ................................................................ 171
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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