MT40A1G4RH-083E Datasheet, PDF (132/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Post Package Repair
Figure 73: hPPR WRA – Repair and Exit
CK_c
CK_t
CMD
BG
BA
ADDR
CKE
DQS_t
DQS_c
DQs1
All Banks
Precharged
and idle state
Te0
ACT
BGf
BAf
Valid
Tf0
Tg0
Tg1
WRA
DES
DES
BGf
N/A
N/A
BAf
N/A
N/A
Valid
N/A
N/A
WL = CWL+AL+PL
Th0
Th1
DES
DES
N/A
N/A
N/A
N/A
N/A
N/A
4nCK
tRCD
hPPR Repair
bit 0 bit 1
bit 6 bit 7
tPGM
hPPR Repair
Tj0
Tj1
DES
REF/DES
N/A
N/A
N/A
N/A
N/A
N/A
tWR _{+tRP + 1nCK}
Tj2
REF/DES
N/A
N/A
N/A
hPPR Repair
Tk0
PRE
Valid
Valid
Valid
Tk1
REF/DES
N/A
N/A
N/A
Tm0
MRSx
Valid
Valid
Valid
(A13 = 0)
Tm1
DES
N/A
N/A
N/A
Tn0
Valid
Valid
Valid
Valid
tPGM_Exit
hPPR Recognition
tPGMPST
hPPR Exit
Normal
mode
Don’t Care
hPPR Row Repair – WR Initiated (REF Commands NOT Allowed)
1. Issue an ACT command with failing BG and BA with the row address to be re-
paired.
2. Issue a WR command with BG and BA of failing row address.
a. The address must be at valid levels, but the address is "Don't Care."
3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7)
after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair.
a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through
bit 7 are LOW.
b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through
bit 7 is HIGH.
1. JEDEC states: All DQs of target DRAM should be LOW for 4^tCK. If HIGH
is driven to all DQs of a DRAM consecutively for equal to or longer than
2^tCK, then DRAM does not conduct hPPR and retains data if REF com-
mand is properly issued; if all DQs are neither LOW for 4^tCK nor HIGH
for equal to or longer than 2^tCK, then hPPR mode execution is un-
known.
c. DQS should function normally.
4. REF commands may NOT be issued at anytime while in PPT mode.
5. Issue PRE after ^tPGM time so that the device can repair the target row during ^tPGM
time.
a. Wait ^tPGM_Exit after PRE to allow the device to recognize the repaired target
row address.
6. Issue MR4[13] 0 command to hPPR mode disable.
a. Wait ^tPGMPST for hPPR mode exit to complete.
b. After ^tPGMPST has expired, any valid command may be issued.
The entire sequence from hPPR mode enable through hPPR mode disable may be re-
peated if more than one repair is to be done.
After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if
the device is to be accessed.
After hPPR mode has been exited, the DRAM controller can confirm if the target row
was repaired correctly by writing data into the target row and reading it back.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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