MT40A1G4RH-083E Datasheet, PDF (340/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
Parameter
Cumulative error across 2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
9 cycles
10 cycles
11 cycles
12 cycles
n = 13, 14 . . . 49,
50 cycles
Symbol
t_ERR2per
t_ERR3per
t_ERR4per
t_ERR5per
t_ERR6per
t_ERR7per
t_ERR8per
t_ERR9per
t_ERR10per
t_ERR11per
t_ERR12per
t_ERRnper
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Min Max Min Max Min Max Min Max
–92
92
–79
79
–69
69
–61
61
–109 109 –94
94
–82
82
–73
73
–121 121 –104 104 –91
91
–81
81
–131 131 –112 112 –98
98
–87
87
–139 139 –119 119 –104 104 –92
92
–145 145 –124 124 –109 109 –97
97
–151 151 –129 129 –113 113 –101 101
–156 156 –134 134 –117 117 –104 104
–160 160 –137 137 –120 120 –107 107
–164 164 –141 141 –123 123 –110 110
–168 168 –144 144 –126 126 –112 112
t_{ERRnper MIN = (1 + 0.68ln[n]) ×} t_{JITper_tot MIN}
t_{ERRnper MAX = (1 + 0.68ln[n]) ×} t_{JITper_tot MAX}
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Notes
DQ Input Timing
Data setup time to
Base (calibrated
t_DS
Refer to DQ Input Receiver Specification section
–
DQS_t, DQS_c
V_REF)
(approximately 0.15^tCK to 0.28^tCK )
Noncalibrated
t_{PDA_S}
minimum of 0.5UI
UI
V_REF
Data hold time from Base (calibrated
t_DH
Refer to DQ Input Receiver Specification section
–
DQS_t, DQS_c
V_REF)
(approximately 0.15^tCK to 0.28^tCK )
Noncalibrated
t_{PDA_H}
minimum of 0.5UI
UI
V_REF
DQ and DM minimum data pulse width
t_DIPW
0.58
–
0.58
–
0.58
–
0.58
–
UI
for each input
DQ Output Timing (DLL enabled)
DQS_t, DQS_c to DQ skew, per group, per
access
t_DQSQ
–
0.16
–
0.16
–
0.16
–
0.17
UI
DQ output hold time from DQS_t, DQS_c
t_QH
0.76
–
0.76
–
0.76
–
0.74
–
UI
Data Valid Window per device: ^tQH -
t_DVWd
0.63
0.63
0.64
0.64
UI
t_{DQSQ each device’s output per UI}
Data Valid Window per device, per pin:
t_DVWp
0.66
–
0.66
–
0.69
–
0.72
–
UI
t_{QH -} t_{DQSQ each device’s output per UI}