MT40A1G4RH-083E Datasheet, PDF (211/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. The example assumes that ^tRAS (MIN) is satisfied at the PRECHARGE command time
(T16) and that ^tRC (MIN) is satisfied at the next ACTIVATE command time (T27).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 152: READ with Auto Precharge and 1^tCK Preamble
T0
T1
T2
T3
T6
T7
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CK_c
CK_t
Command DES
RDA
DES
DES
DES
PRE
DES
DES
DES
DES
DES
DES
DES
DES
ACT
DES
DES
DES
Bank Group
Address
BGa
BGa or
BGb
BGa
Address
Bank a
Col n
BC4 Opertaion
DQS_t,
DQS_c
DQ
BL8 Opertaion
DQS_t,
DQS_c
DQ
t_RTP
Bank a
Col n
RL = AL + CL
t_RP
DO DO DO DO
n n+1 n+2 n+3
DO DO DO DO DO DO DO DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
Bank a
Row b
Time Break
Transitioning Data
Don’t Care
Notes:
1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1^tCK, ^tRTP = 6, ^tRP = 11.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. ^tRTP = 6 setting activated by MR0[A11:9 = 001].
5. The example assumes that ^tRC (MIN) is satisfied at the next ACTIVATE command time
(T18).
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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