MT40A1G4RH-083E Datasheet, PDF (78/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Write Leveling
Figure 21: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2)
CK_c⁵
CK_t
Command MRS²
ODT
diff_DQS⁴
Late Prime DQ¹
DES³
DES
DES
t_MOD
t_WLDQSEN
t_WLMRD
T1
t_WLH
t_WLS
T2
t_WLH
t_WLS
DES
DES
DES NOP DES
DES
DES
t_DQSL6
t_DQSH6
t_DQSL6
t_WLO
t_DQSH6
t_WLO
Early Prime DQ¹
t_WLO
t_WLOE
t_WLO
DES
DES
t_WLOE
Undefined Driving Mode Time Break
Don’t Care
Notes:
1. The device drives leveling feedback on all DQs.
2. MRS: Load MR1 to enter write leveling mode.
3. diff_DQS is the differential data strobe. Timing reference points are the zero crossings.
DQS_t is shown with a solid line; DQS_c is shown with a dotted line.
4. CK_t is shown with a solid dark line; CK_c is shown with a dotted line.
5. DQS needs to fulfill minimum pulse width requirements, ^tDQSH (MIN) and ^tDQSL (MIN),
as defined for regular WRITEs; the maximum pulse width is system dependent.
6. ^tWLDQSEN must be satisfied following equation when using ODT:
• DLL = Enable, then ^tWLDQSEN > ^tMOD (MIN) + DODTLon + ^tADC
• DLL = Disable, then ^tWLDQSEN > ^tMOD (MIN) + ^tAONAS
Write Leveling Mode Exit
Write leveling mode should be exited as follows:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see
~Tc0). Note that from this point on, DQ pins are in undefined driving mode and
will remain undefined, until ^tMOD after the respective MR command (Te1).
2. Drive ODT pin LOW (^tIS must be satisfied) and continue registering LOW (see
Tb0).
3. After R_TT is switched off, disable write leveling mode via the MRS command (see
Tc2).
4. After ^tMOD is satisfied (Te1), any valid command can be registered. (MR com-
mands can be issued after ^tMRD [Td1]).
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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