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MT40A1G4RH-083E Datasheet, PDF (205/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM
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4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 142: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
4 Clocks
tWTR
Bank Group
BGa
Address
BGa or
BGb
Address
Bank
Col n
DQS_t,
DQS_c
DQ
Bank
Col b
RL = 11
tRPRE
tRPST
DO DO DO DO
n n+1 n+2 n+3
WL = 10
tWPRE
tWPST
DI DI DI DI
b b+1 b+2 b+3
Time Break
Transitioning Data
Don’t Care
Notes:
1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0
and WRITE commands at T6.
5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 143: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
2 Clocks
tWTR
Bank Group
BGa
Address
BGa or
BGb
Address
Bank
Col n
DQS_t,
DQS_c
DQ
Bank
Col b
RL = 11
tRPRE
tRPST
tWPRE
tWPST
WL = 9
DO DO DO DO
n n+1 n+2 n+3
DI DI DI DI
b b+1 b+2 b+3
Time Break
Transitioning Data
Don’t Care
Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0),
WRITE preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
205
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