MT40A1G4RH-083E Datasheet, PDF (344/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Parameter
Symbol
Min Max Min Max Min Max Min Max
Delay from start of internal WRITE trans- ^tWTR_S_CRC_D MIN = ^tWTR_S +
action to internal READ command – Dif-
M
greater of (4CK
ferent bank group when CRC and DM are
or 3.75ns)
both enabled
t_{WTR_S_CRC_D}
M₂
READ-to-PRECHARGE time
t_RTP
MIN = ^tWTR_S + greater of (5CK or 3.75ns)
MIN = 1CK + ^tWTR_S_CRC_DM
MIN = greater of 4CK or 7.5ns
CAS_n-to-CAS_n command delay to dif-
ferent bank group
t_{CCD_S}
4
–
4
–
4
–
4
–
CAS_n-to-CAS_n command delay to same
bank group
t_{CCD_L}
MIN = – MIN = – MIN = – MIN = –
greater
greater
greater
greater
of 4CK
of 4CK
of 4CK
of 4CK
or
or
or
or 5ns
6.25ns
5.355ns
5.355ns
Auto precharge write recovery + pre-
charge time
t_{DAL (MIN)}
MIN = WR + ROUNDUP^tRP/^tCK (AVG); MAX = N/A
MRS Command Timing
MRS command cycle time
t_MRD
8
–
8
–
8
–
8
–
MRS command cycle time in PDA mode
t_{MRD_PDA}
MIN = greater of (16nCK, 10ns)
MRS command cycle time in CAL mode
t_{MRD_CAL}
MIN = ^tMOD + ^tCAL
MRS command update delay
t_MOD
MIN = greater of (24nCK, 15ns)
MRS command update delay in PDA
mode
t_{MOD_PDA}
MIN = ^tMOD
MRS command update delay in CAL
mode
t_{MOD_CAL}
MIN = ^tMOD + ^tCAL
MRS command to DQS drive in preamble
training
t_SDO
MIN = ^tMOD + 9ns
MPR Command Timing
Multipurpose register recovery time
t_MPRR
MIN = 1CK
Multipurpose register write recovery time ^tWR_MPRR
MIN = ^tMOD + AL + PL
CRC Error Reporting Timing
CRC error to ALERT_n latency
t_{CRC_ALERT}
3
13
3
13
3
13
3
13
CRC ALERT_n pulse width
t_{CRC_ALERT_P 6}
10
6
10
6
10
6
10
W
Unit
CK
Notes
7, 8, 9,
10, 1
CK 7, 8, 9,
11, 1
CK
1
CK
CK
15
CK
CK
CK
1
CK
CK
1
CK
CK
CK
ns
CK