MT40A1G4RH-083E Datasheet, PDF (239/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
6. The write recovery time (^tWR) is referenced from the first rising clock edge after the last
write data shown at T13. ^tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
Figure 189: WRITE (BC4-Fixed) to Auto PRECHARGE with 1^tCK Preamble
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T22
T23
T24
T25
T26
CK_c
CK_t
Command WRITE
DES
BGa, Bank b
Col n
Address
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DQ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
WL = AL + CWL = 9
2 Clocks
t_{WR = 12}
t_RP
DI DI DI DI
n n+1 n+2 n+3
Time Break
Transitioning Data
Don’t Care
Notes:
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1^tCK, ^tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
6. The write recovery time (^tWR) is referenced from the first rising clock edge after the last
write data shown at T11. ^tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
239
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