LAN8810 Datasheet, PDF (9/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
TABLE 2-4: ETHERNET PINS
Num Pins
Name
Ethernet TX/
1
RX Positive
Channel 0
Ethernet TX/
1
RX Negative
Channel 0
Ethernet TX/
1
RX Positive
Channel 1
Ethernet TX/
1
RX Negative
Channel 1
Ethernet TX/
1
RX Positive
Channel 2
Ethernet TX/
1
RX Negative
Channel 2
Ethernet TX/
1
RX Positive
Channel 3
Ethernet TX/
1
RX Negative
Channel 3
1
External PHY
Bias Resistor
Symbol
TR0P
TR0N
TR1P
TR1N
TR2P
TR2N
TR3P
TR3N
ETHRBIAS
Buffer
Type
AIO
Description
Transmit/Receive Positive Channel 0.
AIO
Transmit/Receive Negative Channel 0.
AIO
Transmit/Receive Positive Channel 1.
AIO
Transmit/Receive Negative Channel 1.
AIO
Transmit/Receive Positive Channel 2.
AIO
Transmit/Receive Negative Channel 2.
AIO
Transmit/Receive Positive Channel 3.
AIO
Transmit/Receive Negative Channel 3.
AI
Used for the internal bias circuits. Connect to an
external 8.06K 1.0% resistor to ground.
TABLE 2-5: JTAG PINS
Num Pins
1
1
Name
JTAG Test
Data Out
JTAG Test
Data Input
1
JTAG Test
Clock
JTAG Test
1
Mode Select
Symbol
TDO
TDI
TCK
TMS
Buffer
Type
VO8
Description
JTAG (IEEE 1149.1) data output.
VIS
(PU)
VIS
(PD)
VIS
(PU)
JTAG (IEEE 1149.1) data input.
Note: When not used, tie this pin to
VDDVARIO.
JTAG (IEEE 1149.1) test clock.
Note: When not used, tie this pin to VSS.
JTAG (IEEE 1149.1) test mode select.
Note: When not used, tie this pin to
VDDVARIO.
 2009-2015 Microchip Technology Inc.
DS00001870B-page 9